`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:02:58 01/03/2021
// Design Name:   mem_ctrl
// Module Name:   D:/_FPGA/ARC_2020/Lab4_Cache/sword4-test-bench/test/test_mem.v
// Project Name:  sword4-test-bench
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: mem_ctrl
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_mem;

	// Inputs
	reg clk;
	reg rst;
	reg [31:0] mem_req_addr;
	reg [31:0] mem_req_data;
	reg mem_req_wen;
	reg mem_req_valid;

	// Outputs
	wire mem_resp_valid;
	wire [31:0] mem_resp_data;

	// Instantiate the Unit Under Test (UUT)
	imem_ctrl uut (
		.clk(clk), 
		.rst(rst), 
		.mem_req_addr(mem_req_addr), 
		.mem_req_data(mem_req_data), 
		.mem_req_wen(mem_req_wen), 
		.mem_req_valid(mem_req_valid), 
		.mem_resp_valid(mem_resp_valid), 
		.mem_resp_data(mem_resp_data)
	);
	
	always begin
		#10 clk = ~clk;
	end 

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 1;
		mem_req_addr = 0;
		mem_req_data = 0;
		mem_req_wen = 0;
		mem_req_valid = 0;

		// Wait 100 ns for global reset to finish
		#100;
		rst = 0;
		
		mem_req_addr = 0;
		mem_req_data = 32'b0;
		mem_req_wen = 0;
		mem_req_valid = 1;
		
		#160;
		mem_req_wen = 0;
		mem_req_valid = 0;		
		
		#20;
		mem_req_addr = 0;
		mem_req_data = 32'h5a5a5a5a;
		mem_req_wen = 1;
		mem_req_valid = 1;
		
        
		// Add stimulus here

	end
      
endmodule

